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STM32F103C8T6 Blue pill цоколёвка

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STM32F103x8, STM32F103xB Pinouts and pin description

Table 5. Medium-density STM32F103xx pin definitions
Pins Pin name Type
(*1)
I/O Level
(*2)
Main
function(3) (after reset)
Alternate functions(4)
LFBGA100 UFBG100 LQFP48/UFQFPN48 TFBGA64 LQFP64 LQFP100 VFQFPN36 Default Remap
A3 B2 - - - 1 - PE2 I/O FT PE2 TRACECK -
B3 A1 - - - 1 - PE3 I/O FT PE3 TRACED0 -
C3 B1 - - - 3 - PE4 I/O FT PE4 TRACED1 -
D3 C2 - - - 4 - PE5 I/O FT PE5 TRACED2 -
E3 D2 -     5 - PE6 I/O FT PE6 TRACED3  
B2 E2 1 B2 1 6 - VBAT S - VBAT - -
                         

Pins

Pin name

Type
(*1)
I/O Level
(*2)

Main
function(3) (after reset)

Alternate functions(4)

LFBGA100

UFBG100

LQFP48/UFQFPN48

TFBGA64

LQFP64

LQFP100

VFQFPN36

Default

Remap

 

 

 

 

 

 

-

 

 

-

 

-

-

A2

C1

2

A2

2

7

-

PC13-TAMPER-
rtc(5)

I/O

-

PC13(6)

TAMPER-RTC

-

A1

D1

3

A1

3

8

-

PC14-OSC32_IN(5)

I/O

-

PC14(6)

OSC32_IN

-

B1

E1

4

B1

4

9

-

PC15-
OSC32_OUT(5)

I/O

-

PC15(6)

OSC32_OUT

-

C2

F2

-

-

-

10

-

VSS_5

S

-

VSS_5

-

-

D2

G2

-

-

-

11

-

VDD_5

S

-

VDD_5

-

 

C1

F1

5

C1

5

12

2

OSC_IN

I

-

OSC_IN

-

PD0(7)

D1

G1

6

D1

6

13

3

OSC_OUT

O

-

OSC_OUT

 

PD1(7)

E1

H2

7

E1

7

14

4

NRST

I/O

-

NRST

-

-

F1

H1

-

E3

8

15

-

PC0

I/O

-

PC0

ADC12_IN10

-

F2

J2

-

E2

9

16

-

PC1

I/O

-

PC1

ADC12_IN11

-

E2

J3

-

F2

10

17

-

PC2

I/O

-

PC2

ADC12_IN12

-

F3

K2

-

-(8)

11

18

-

PC3

I/O

-

PC3

ADC12_IN13

-

G1

J1

8

F1

12

19

5

VSSA

S

-

VSSA

-

-

H1

K1

-

-

-

20

-

VREF-

S

-

VREF-

-

-

J1

L1

-

G1(8)

-

21

-

VREF+

S

-

VREF+

-

-

K1

M1

9

H1

13

22

6

VDDA

S

-

VDDA

-

-

G2

L2

10

G2

14

23

7

PA0-WKUP

I/O

-

PA0

WKUP/
USART2 CTS(9)/ ADC12 IN0/ TIM2 CH1
ETR(9)

-

H2

M2

11

H2

15

24

8

PA1

I/O

-

PA1

USART2_RTS(9)/ ADC12 IN1/ TIM2_CH2(9)

-

J2

K3

12

F3

16

25

9

PA2

I/O

-

PA2

USART2_TX(9)/ ADC12 IN2/ TIM2_CH3(9)

-

K2

L3

13

G3

17

26

10

PA3

I/O

-

PA3

USART2 RX(9)/ ADC12_IN3/ TIM2_CH4(9)

-

E4

E3

-

C2

18

27

-

VSS_4

S

-

VSS_4

-

-

F4

H3

-

D2

19

28

-

VDD_4

S

-

VDD_4

-

-

G3

M3

14

H3

20

29

11

PA4

I/O

-

PA4

SPI1 nss(9)/ USART2 CK(9)/ ADC12_IN4

-

H3

K4

15

F4

21

30

12

PA5

I/O

-

PA5

SPI1 SCK(9)/ ADC12_IN5

-

J3

L4

16

G4

22

31

13

PA6

I/O

-

PA6

SPI1 MISO(9)/ ADC12_IN6/ TIM3_CH1(9)

TIM1_BKIN

K3

M4

17

H4

23

32

14

PA7

I/O

-

PA7

SPI1 MOSI(9)/ ADC12_IN7/ TIM3_CH2(9)

TIM1_CH1N

G4

K5

-

H5

24

33

 

PC4

I/O

-

PC4

ADC12_IN14

-

H4

L5

-

H6

25

34

 

PC5

I/O

-

PC5

ADC12_IN15

-

J4

M5

18

F5

26

35

15

PB0

I/O

-

PB0

ADC12_IN8/
TIM3_CH3(9)

TIM1_CH2N

K4

M6

19

G5

27

36

16

PB1

I/O

-

PB1

ADC12_IN9/
TIM3_CH4(9)

TIM1_CH3N

G5

L6

20

G6

28

37

17

PB2

I/O

FT

PB2/BOOT1

-

-

H5

M7

-

-

-

38

-

PE7

I/O

FT

PE7

-

TIM1_ETR

J5

L7

-

-

-

39

-

PE8

I/O

FT

PE8

-

TIM1_CH1N

K5

M8

-

-

-

40

-

PE9

I/O

FT

PE9

-

TIM1_CH1

G6

L8

-

-

-

41

-

PE10

I/O

FT

PE10

-

TIM1_CH2N

H6

M9

-

-

-

42

-

PE11

I/O

FT

PE11

-

TIM1_CH2

J6

L9

-

-

-

43

-

PE12

I/O

FT

PE12

-

TIM1_CH3N

K6

M10

-

-

-

44

-

PE13

I/O

FT

PE13

-

TIM1_CH3

G7

M11

-

-

-

45

-

PE14

I/O

FT

PE14

-

TIM1_CH4

H7

M12

-

-

-

46

-

PE15

I/O

FT

PE15

-

TIM1_BKIN

J7

L10

21

G7

29

47

-

PB10

I/O

FT

PB10

I2C2_SCL/
USART3_TX(9)

TIM2_CH3

K7

L11

22

H7

30

48

-

PB11

I/O

FT

PB11

I2C2_SDA/
USART3_RX(9)

TIM2_CH4

E7

F12

23

D6

31

49

18

VSS_1

S

-

VSS_1

-

-

F7

G12

24

E6

32

50

19

VDD_1

S

-

VDD_1

-

-

K8

L12

25

H8

33

51

-

PB12

I/O

FT

PB12

SPI2 NSS/ I2C2_SMBAl/ USART3 CK(9)/ TIM1_BKIN(9)

-

J8

K12

26

G8

34

52

-

PB13

I/O

FT

PB13

SPI2 SCK/ USART3_CTS(9)/ TIM1_CH1N (9)

-

H8

K11

27

F8

35

53

-

PB14

I/O

FT

PB14

SPI2 MISO/ USART3_RTS(9) TIM1_CH2N (9)

-

G8

K10

28

F7

36

54

-

PB15

I/O

FT

PB15

SPI2 MOSI/ TIM1_CH3N(9)

-

K9

K9

-

-

-

55

-

PD8

I/O

FT

PD8

-

USART3_TX

J9

K8

-

-

-

56

-

PD9

I/O

FT

PD9

-

USART3_RX

H9

J12

-

-

-

57

-

PD10

I/O

FT

PD10

-

USART3_CK

G9

J11

-

-

-

58

-

PD11

I/O

FT

PD11

-

USART3_CTS

K10

J10

-

-

-

59

-

PD12

I/O

FT

PD12

-

TIM4 CH1 / USART3_RTS

J10

H12

-

-

-

60

-

PD13

I/O

FT

PD13

-

TIM4_CH2

H10

H11

-

-

-

61

-

PD14

I/O

FT

PD14

-

TIM4_CH3

G10

H10

-

-

-

62

-

PD15

I/O

FT

PD15

-

TIM4_CH4

F10

E12

-

F6

37

63

-

PC6

I/O

FT

PC6

-

TIM3_CH1

E10

E11

 

E7

38

64

-

PC7

I/O

FT

PC7

-

TIM3_CH2

F9

E10

 

E8

39

65

-

PC8

I/O

FT

PC8

-

TIM3_CH3

E9

D12

-

D8

40

66

-

PC9

I/O

FT

PC9

-

TIM3_CH4

D9

D11

29

D7

41

67

20

PA8

I/O

FT

PA8

USART1 CK/ TIM1 CH1(9)/ MCO

-

C9

D10

30

C7

42

68

21

PA9

I/O

FT

PA9

USART1 TX(9)/ TIM1_CH2(9)

-

D10

C12

31

C6

43

69

22

PA10

I/O

FT

PA10

USART1 RX(9)/ TIM1_CH3(9)

-

C10

B12

32

C8

44

70

23

PA11

I/O

FT

PA11

USART1_CTS/
canrx(9)/
USBDM/
TIM1_CH4(9)

-

B10

A12

33

B8

45

71

24

PA12

I/O

FT

PA12

USART1 RTS/
CANTX(9)
/USBDP
TIM1_ETR(9)

-

A10

A11

34

A8

46

72

25

PA13

I/O

FT

JTMS/SWDIO

-

PA13

F8

C11

-

-

-

73

-

Not connected

-

E6

F11

35

D5

47

74

26

VSS_2

S

-

VSS_2

-

-

F6

G11

36

E5

48

75

27

VDD_2

S

-

VDD_2

-

-

A9

A10

37

A7

49

76

28

PA14

I/O

FT

JTCK/SWCLK

-

PA14

A8

A9

38

A6

50

77

29

PA15

I/O

FT

JTDI

-

TIM2 CH1 ETR/PA15 /SPI1_NSS

B9

B11

-

B7

51

78

 

PC10

I/O

FT

PC10

-

USART3_TX

B8

C10

-

B6

52

79

 

PC11

I/O

FT

PC11

-

USART3_RX

C8

B10

-

C5

53

80

 

PC12

I/O

FT

PC12

-

USART3_CK

D8

C9

-

C1

-

81

2

PD0

I/O

FT

PD0

-

CANRX

E8

B9

-

D1

-

82

3

PD1

I/O

FT

PD1

-

CANTX

B7

C8

 

B5

54

83

-

PD2

I/O

FT

PD2

TIM3_ETR

-

C7

B8

-

-

-

84

-

PD3

I/O

FT

PD3

-

USART2_CTS

D7

B7

-

-

-

85

-

PD4

I/O

FT

PD4

-

USART2_RTS

B6

A6

-

-

-

86

-

PD5

I/O

FT

PD5

-

USART2_TX

C6

B6

-

-

-

87

-

PD6

I/O

FT

PD6

-

USART2_RX

D6

A5

-

-

-

88

-

PD7

I/O

FT

PD7

-

USART2_CK

A7

A8

39

A5

55

89

30

PB3

I/O

FT

JTDO

-

TIM2 CH2 / PB3
TRACESWO
SPI1_SCK

A6

A7

40

A4

56

90

31

PB4

I/O

FT

JNTRST

-

TIM3 CH1/ PB4/
SPI1_MISO

C5

C5

41

C4

57

91

32

PB5

I/O

 

PB5

I2C1_SMBAl

TIM3_CH2 / SPI1_MOSI

B5

B5

42

D3

58

92

33

PB6

I/O

FT

PB6

I2C1 SCL(9)/ TIM4_CH1(9)

USART1_TX

A5

B4

43

C3

59

93

34

PB7

I/O

FT

PB7

I2C1 SDA(9)/ TIM4_CH2(9)

USART1_RX

D5

A4

44

B4

60

94

35

BOOT0

I

 

BOOT0

-

-

B4

A3

45

B3

61

95

-

PB8

I/O

FT

PB8

TIM4_CH37 8 (9)

I2C1 SCL / CANRX

A4

B3

46

A3

62

96

-

PB9

I/O

FT

PB9

TIM4_CH4(9)

I2C1 SDA/ CANTX

D4

C3

-

-

-

97

-

PE0

I/O

FT

PE0

TIM4_ETR

-

C4

A2

-

-

-

98

-

PE1

I/O

FT

PE1

-

-

E5

D3

47

D4

63

99

36

VSS_3

S

-

VSS_3

-

-

F5

C4

48

E4

64

100

1

VDD_3

S

-

VDD_3

-

-

 

  1. I = input, O = output, S = supply.
  2. FT = 5 V tolerant.
  3. Function availability depends upon the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they are called SPI1 and USART1 and USART2, respectively. Refer to Table 2.
  4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
  5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive a LED).
  6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.
  7. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48, UFQFP48 and LQFP64 packages, and C1 and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.
    The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
  8. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.
  9. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com.


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